Method and apparatus for pre-charging data lines in a memory cell array

ABSTRACT

Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 13/081,260, filed Apr. 6, 2011. This application is incorporated by reference herein in its entirety and for all purposes.

TECHNICAL FIELD

Embodiments of the present invention relate generally to semiconductor memory, and more particularly in one or more of the illustrated embodiments, to semiconductor memory utilizing a technique for increasing the speed capability and storage capacity of the memory.

BACKGROUND OF THE INVENTION

Associated with the rapid progress of semiconductor integration circuit techniques and the development of a higher integration of semiconductor elements, a technological revolution for semiconductor memory devices has been in progress with the aim of gaining larger capacity and further miniaturization.

A data read operation performed in a memory device requires pre-charging the data lines, which are commonly referred to in conventional flash devices as “bit lines” (in light of this convention, the term “bit lines” will be used hereinafter in the examples). The reason is that, to confirm whether a memory cell is in an erase state “1” or program state “0”, a verification of a change in potential is difficult unless the bit line is provided with a certain level of potential. A common practice is to apply a pre-charge voltage to increase the voltage of the bit line to a predetermined value in advance, followed by detecting a change in the voltage of the bit line when the bit line is applied to a memory cell by comparing the voltage of the bit line with the pre-charge voltage used as a reference.

One recent problem accompanying large capacity memory (on the order of gigabytes) is the extension of the length of bit lines. This causes the resistance value R of the bit line to increase and the parasitic capacitance C between the bit lines to increase, thus increasing a time constant RC of the bit lines. An increase in the time constant RC results in increasing the time period required to drive the bit lines to a voltage, for example, to a pre-charge voltage. Because pre-charging of bit lines is performed for most memory access operations, and increase in the time to pre-charge bit lines may be significant and have a negative effect on memory performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified functional block diagram of a bit line pre-charge circuit according to an embodiment of the present invention.

FIG. 2 is a simplified functional block diagram of a voltage generator according to an embodiment of the present invention for the bit line pre-charge circuit of FIG. 1.

FIG. 3 is a simplified schematic diagram of a voltage generator according to an embodiment of the present invention for the bit line pre-charge circuit of FIG. 1.

FIG. 4 is a simplified schematic diagram of a dummy array column driver and dummy cell array according to an embodiment of the present invention.

FIG. 5 is a simplified schematic diagram of a voltage detector according to an embodiment of the present invention for the bit line pre-charge circuit of FIG. 1.

FIG. 6 is a simplified block diagram of a memory according to various embodiments of the present invention.

DETAILED DESCRIPTION

In the following description, certain details are set forth below to provide a sufficient understanding of the invention. However, it will be clear to one skilled in the art that the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 1 illustrates a bit line pre-charge circuit 100 according to an embodiment of the present invention. Voltage generator 115 generates an output voltage VOUT based at least in part on a target bit line voltage VREF 110 provided to the voltage generator 115. The VOUT voltage is provided to a voltage driver 125 and is used to generate a variable clamp voltage blclamp, which may be used to couple bit lines in cell array 135 through array column driver 130 to a pre-charge voltage during pre-charge operations. The blclamp voltage is variable based at least in part on the magnitude of the VOUT voltage from the voltage generator 115. Cell array 135, for example, may have k bit lines 133. The blclamp voltage may be further provided to dummy array column driver 140 to couple the pre-charge voltage to dummy bit lines 142 in dummy cell array 145. Although the voltage driver 125 is illustrated in FIG. 1 as a separate functional block, in some embodiments it may be included in the voltage generator 115 or the array column driver 130 and the dummy column driver 140.

In various embodiments of the present invention, the dummy column driver 140, dummy bit line 142, and dummy cell array 145 may be designed such that dummy bit line 142 reproduces the parasitic RC characteristic of bit lines 133. In one embodiment, dummy column driver 140, dummy bit line 142, and dummy cell array 145 may be the same circuit and interconnect design as array column driver 130, bit lines 133, and cell array 135. In another embodiment, dummy column driver 140, dummy bit line 142, and dummy cell array 145 may be the same design with a different shape or layout (e.g, to save die area). In further embodiments of the present invention, dummy column driver 140, dummy bit line 142, and dummy cell array 145 may be repeated (i.e., reproduced or copied) multiple times throughout the memory die. As readily understood to one of ordinary skill in the art, dummy column driver 140, dummy bit line 142, and dummy cell array 145 may comprise any equivalent network such that dummy bit line 142 has the same parasitic resistance and capacitance as bit lines 133 in cell array 135. Other combinations and permutations are possible. For example, depending upon the layout and size of the memory die, there will be a different number of total number of dummy bit lines 142 and different ratios of dummy bit lines 142 to bit lines 133.

A voltage detector 150 is coupled to at least some bit lines 142 of the dummy cell array 145 to receive a bit line sample voltage bl_sample. The voltage detector 150 further receives the VREF voltage and is configured to detect a difference between the bl_sample voltage and the VREF voltage and provide an output signal OFFSET based at least in part on the difference. The OFFSET signal is provided to the voltage generator 115. The bl_sample voltage may be taken from various points along the bit lines 142, for example, at an end node which is the point on the bit line 142 furthest from dummy array column driver 140.

As will be described in more detail below, the voltage generator 115 may adjust the magnitude of the VOUT voltage (and thereby variably adjust the voltage of the blclamp voltage provided to the array column driver 130 and the dummy array column driver 140) based at least in part on the OFFSET signal, for example, so that the bl_sample voltage is closer in magnitude to the VREF voltage. For example, as different memory cells along the length of bit lines 133 in cell array 135 are accessed, the parasitic RC characteristic of bit lines 133 change. By adjusting the VOUT voltage and providing an adjusted blclamp voltage to the array column driver 130, the parasitic RC delay effects of the bit lines 133 of the cell array 135 may be compensated. That is, because the dummy array column driver 140 and the dummy cell array 145 models the array column driver 130 and the cell array 135, respectively, and the dummy bit lines 142 model the parasitic RC characteristic of bit lines 133, the adjusted blclamp voltage (also provided to the array column driver 130) based on the difference between VREF and the bl_sample voltage may compensate for the effects on the bit lines 133, as modeled by bit line 142.

FIG. 2 illustrates a voltage generator 115 according to an embodiment of the present invention. The voltage generator 115 includes a voltage generator stage 118 and a voltage adder stage 120. The voltage generator stage 118 receives the VREF voltage and generates a VREF′ voltage which is provided to the voltage adder stage 120. Based on the OFFSET signal, the voltage adder stage 120 provides a voltage that is summed with the VREF′ voltage to provide the VOUT voltage. As a result, the VOUT voltage may be adjusted based on the OFFSET signal, for example, to compensate for a voltage difference between the VREF voltage and a bl_sample voltage indicative of a bit line voltage of a dummy bit line.

FIG. 3 illustrates a voltage generator 115 according to another embodiment of the present invention. In voltage generator 115, differential amplifier 212 receives target bit line voltage VREF 110 and a feedback voltage Vfb from voltage adder 120. Differential amplifier 212 may be a circuit that multiplies the difference between two inputs by a constant factor called the gain (e.g., operational amplifier or op-amp). The output of differential amplifier 212 is coupled to transistor N1 configured as a diode. The voltage adder 120 is coupled to transistor N1 and provides the Vfb voltage to the differential amplifier 212 having a magnitude based at least in part on the OFFSET signal. The OFFSET signal adjusts a current provided by current source 214 to change the Vfb voltage, thereby adjusting the VOUT voltage based at least in part on the OFFSET signal. The magnitude of the Vfb voltage is Vfb=VREF+VRc, where VRc is dependent on the current provided by the current source 214. The magnitude of the VOUT voltage is VOUT=VREF+VRc+Vgs,N1. Vgs,N1 is the gate-source voltage of transistor N1 when Ids,N1=Idn, where Ids,N1 is the current flowing through the drain and source of transistor N1, and Idn=VREF/Ra. The VRc component, as previously discussed, is provided by voltage adder 120 and is based at least in part on the OFFSET signal.

As also previously discussed, the VOUT voltage is provided to a voltage driver, for example, voltage driver 125 which provides a clamp voltage blclamp (based on the VOUT voltage) to array column driver 130 and dummy array column driver 140.

FIG. 4 illustrates a dummy array column driver 140 and a dummy cell array 145 according to an embodiment of the present invention. FIG. 4 further illustrates an array column driver 130 and cell array 135. Both the array column driver 130 and the dummy array column driver 140 receive the blclamp voltage. Array column driver 130 is comprised of two or more transistors N3 and N5 which may receive blclamp at their gates. Coupled to transistors N3 and N5 are transistors N2 and N4 which receive blpre at their gates and Vreg. The blpre signal is a conventional bit line pre-charge enable signal that activates transistors N2 and N4 during a pre-charge operation. A pre-charge voltage source Vreg provides a pre-charge voltage to the bit lines of the cell array 135 through transistors N2, N3 and N4, N5. In the embodiment illustrated in FIG. 4, the dummy array column driver 140 includes transistors ND1, ND2 that are similar to transistors N2, N3 and N4, N5 of the array column driver 140.

Cell array 135 comprises bit lines 232-234. Bit lines 232-234 are represented by a simplified model for parasitic RC characteristic of a (long) metal bit line. Nodes bl_b are nearest to array column driver 130 and nodes bl_t are furthest from array column driver 130. Rbl is the parasitic resistance of the bit lines. Cbl is the parasitic capacitance of the bit lines. Dummy array column driver 140 and dummy cell array 145 may be designed to replicate the parasitic RC characteristics of bit lines 232-234 of cell array 135 in bit line 236 of dummy cell array 145.

As previously discussed, by replicating the parasitic RC characteristics of bit lines 232-234 using bit line 236, a sample voltage bl_sample taken from the bit line 236 can be used to feedback voltage information to a voltage generator, for example, voltage generator 115. The voltage generator may adjust the blclamp voltage provided to the array column driver 130 and the dummy array column driver 140 based on the feedback voltage to compensate for any difference between the VREF and bl_sample voltages, and thereby compensate for any difference between the VREF voltage and the voltage of bit lines 232-234, as modeled by bit line 236. For example, in some embodiments, the transistors N3 and N5, are of the same dimensions as transistor N1 of the voltage generator of FIG. 3. In this manner, the threshold voltages Vt of transistors N1, N3, and N5 are similar. As a result, where the blclamp voltage is equal to VOUT, and VOUT=VREF+VRc+Vgs,N1, the voltage applied by Vreg through the transistors N3 and N5 of the array column driver 130 and the transistor ND1 of the dummy array column driver 140 to the bit lines 232, 234 and dummy bit line 236 is VREF+VRc, where VREF is the target bit line voltage and VRc is the added voltage from the voltage adder 120 based on the difference between VREF and bl_sample. With a higher blclamp voltage, the transistors N3 and N5 of the array column driver 130 and the transistor N5 of the dummy column driver 140 are more conductive allowing the Vreg supply to drive the bit lines harder. That is, the coupling of the Vreg to the bit lines may be based at least in part on a voltage difference between a target bit-line voltage VREF and a voltage of at least one bit line being pre-charged bl_sample.

FIG. 5 illustrates a voltage detector 150 according to an embodiment of the present invention. Voltage detector 150 receives bl_sample in differential amplifier 252. Differential amplifier 252 is configured as a buffer to buffer the bl_sample voltage, which is applied to a node of resistance Rb. Resistance Rb is coupled through transistor N6 to a voltage supply Vcc. Transistor N6, for example, may be a p-type field effect transistor (FET). Differential amplifier 258 is coupled to the gate of transistor N6. Differential amplifier 258 receives target bit line voltage VREF 110 and feedback 260. A current mirror 256 is coupled to receive current Ib as an input current.

In operation, the output of current mirror 256 is mirrored from the Ib current, which may be given by: Ib=Vdiff/Rb, where Vdiff=VREF−bl_sample. Accordingly, Ib is reflective of the voltage difference between VREF and bl_sample. The relationship between the Ib current and Vdiff is that the Ib current increases as the difference between the VREF and bl_sample voltages increases and the Ib current decreases as the difference between the VREF and bl_sample voltages decreases. The Ib current of the current mirror 256 is provided to voltage generator 115 as the OFFSET signal. For example, with reference to the embodiment of the voltage generator 115 illustrated by FIG. 3, the output of current mirror 256, Ib, may be received in voltage adder 120 as an input to current source 214. Current source 214 may provide a pull down current, IOFFSET, which may be given by: IOFFSET=K*Ib, where K is the number of bit lines. Current source 214 is coupled to an input of differential amplifier 212. In operation, current source 214 adds voltage which is a function of the difference between VREF and bl_sample: Vdiff=K*Ib*RC=IOFFSET*RC. So, at input Vfb of differential amplifier 212, Vfb=VREF+Vdiff. Hence, the output of voltage generator 115 may be given by: VOUT=VREF+Vgs,N1+Vdiff. As a result, in response to a relatively large Ib (i.e., indicating a relatively large difference between VREF and bl_sample) a relatively large voltage is added to VOUT, whereas in response to a relatively small Ib (i.e., indicating a relatively small difference between VREF and bl_sample), a relatively small voltage is added to VOUT. When Ib is zero, indicating VREF and bl_sample are equal, the voltage adder 120 does not add any voltage to VOUT.

Due to the dynamic nature of a bit line pre-charge circuit having feedback based on the voltage of dummy bit lines modeling actual bit lines, transient response during bit line pre-charge may be improved. That is, when the bit lines are initially pre-charged, the blclamp voltage which is based on VOUT from the voltage generator 115 and applied to the array column driver 130 and the dummy array column driver 140 may be relatively high to make transistors N3 and N5 of the array column driver 130 and transistor N5 of the dummy array column driver 140 more conductive to allow greater drive from the Vreg supply. As the bl_sample voltage increases to the target pre-charge voltage VREF, the blclamp voltage may be reduced to VREF+Vtnl, that is, the additional voltage provided by the voltage adder 120 reduces to zero because the difference between VREF and bl_sample becomes zero.

FIG. 6 illustrates a memory according to some embodiments of the present invention. The memory 300 includes an array 302 of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other type of memory cells. The memory system 300 includes a command decoder 306 that receives memory commands through a command bus 308 and generates corresponding control signals within the memory system 300 to carry out various memory operations. The command decoder 306 responds to memory commands applied to the command bus 308 to perform various operations on the memory array 302. For example, the command decoder 306 is used to generate internal control signals to read data from and write data to the memory array 302. Row and column address signals are applied to the memory system 300 through an address bus 320 and provided to an address latch 310. The address latch then outputs a separate column address and a separate row address.

The row and column addresses are provided by the address latch 310 to a row address decoder 322 and a column address decoder 328, respectively. The column address decoder 328 selects bit lines extending through the array 302 corresponding to respective column addresses. The column address decoder 328 includes a bit line pre-charge circuit 332 according to an embodiment of the present invention. As previously discussed, the bit line pre-charge circuit 332 is configured to generate bit line pre-charge voltage that may be adjusted to compensate for a voltage difference between a voltage of the bit lines and a target bit line voltage. The row address decoder 322 is connected to word line driver 324 that activates respective rows of memory cells in the array 302 corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry 330 to provide read data to a data output buffer 334 via an input-output data bus 340. Write data are applied to the memory array 302 through a data input buffer 344 and the memory array read/write circuitry 330.

Memory systems in accordance with embodiments of the present invention may be used in any of a variety of electronic devices including, but not limited to, computing systems, electronic storage systems, cameras, phones, wireless devices, displays, chip sets, set top boxes, or gaming systems.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, the invention is not limited to a specific memory technology and may be applied to several different memory technologies, such as non-volatile memories (e.g., NOR-type flash) and volatile memories (e.g., dynamic random access memory (DRAM), including double data rate (DDR) synchronous dynamic random access memory (SDRAM). As another example, instead of using current Ib in voltage detector 150 and voltage adder 120, a voltage may be generated, and Vdiff used directly or Vdiff derived/generated. Accordingly, the invention is not limited except as by the appended claims. 

What is claimed is:
 1. An apparatus, comprising: a voltage detector configured to receive a model bit line voltage of a model bit line and to receive a reference voltage, and determine a difference between the model bit line voltage and the reference voltage; and a voltage generator coupled to the voltage detector and configured to adjust a voltage provided to a memory array bit line based at least in part on the difference between the model bit line voltage and the reference voltage.
 2. The apparatus of claim 1, wherein the model bit line is configured to model electrical characteristics of the memory array bit line.
 3. The apparatus of claim 1, further comprising: a voltage driver coupled to the voltage generator and configured to provide the voltage to the memory array bit line and the model bit line.
 4. The apparatus of claim 1, wherein the voltage detector comprises: a differential amplifier configured to receive the reference voltage and a feedback voltage, and provide an output based on the difference therebetween; a transistor coupled to the differential amplifier and configured to receive the output from the differential amplifier and receive the model bit line voltage; and a current mirror coupled to the transistor and configured to provide a current indicative of the difference between the model bit line voltage and the reference voltage.
 5. The apparatus of claim 4, wherein the current indicative of the difference between the model bit line voltage and the reference voltage is provided to the voltage generator.
 6. The apparatus of claim 1, wherein the voltage generator comprises: a voltage generator stage configured to provide a first voltage based on the reference voltage; and a voltage adder stage coupled to the voltage generator and configured to provide a second voltage, the second voltage based on the first voltage and the difference between the model bit line voltage and the reference voltage.
 7. The apparatus of claim 6, further comprising a voltage driver coupled to the voltage generator and configured to receive the second voltage and provide a voltage based thereon.
 8. The apparatus of claim 7, further comprising a model array column driver coupled to the model bit line, wherein the model array column driver is coupled to the voltage driver and configured to provide the adjusted driver voltage to the model bit line.
 9. The apparatus of claim 7, further comprising a memory array column driver coupled to the memory array bit line, wherein the memory array column driver is coupled to the voltage driver and configured to provide the adjusted driver voltage to the memory array bit line.
 10. An apparatus, comprising: a voltage detector coupled to a model bit line and configured to determine a difference between a model bit line voltage and a reference voltage, and provide the difference as an offset signal, wherein the model bit line models electrical characteristics of a memory array bit line; and a voltage generator coupled to the voltage detector and configured to provide an output voltage based on the offset signal and a reference voltage.
 11. The apparatus of claim 10, further comprising: a voltage driver coupled to the voltage generator and configured to provide a voltage to the memory array bit line and the model bit line, wherein the voltage is based on the output voltage.
 12. The apparatus of claim 10, wherein the voltage generator comprises a voltage adder stage configured to receive the offset voltage and sum the offset voltage with the reference voltage to provide the voltage.
 13. The apparatus of claim 11, further comprising a model bit line driver coupled to the voltage driver and configured to provide a pre-charge voltage to the model bit line based on the output voltage.
 14. The apparatus of claim 13, wherein a level of the output voltage affects a level of the pre-charge voltage provided to the model bit line.
 15. A method, comprising: determining a voltage difference between a model bit line voltage of a model bit line and a reference voltage; and adjusting a voltage provided to a memory array bit line based at least in part on the voltage difference between the model bit line voltage and the reference voltage.
 16. The method of claim 15, further comprising providing the voltage to the model bit line.
 17. The method of claim 15, further comprising providing a pre-charge voltage to the memory array bit line based on the voltage.
 18. The method of claim 15, wherein determining a voltage difference between a model bit line voltage and a reference voltage comprises: determining a difference between the model bit line voltage and the reference voltage; and providing an offset signal indicative of the voltage difference between the model bit line voltage and the reference voltage.
 19. The method of claim 15, further comprising providing the voltage difference between the model bit line and the reference voltage to a voltage generator.
 20. The method of claim 15, wherein adjusting a voltage provided to a memory array bit line based at least in part on the voltage difference between the model bit line voltage and the reference voltage comprises: receiving the reference voltage; and summing the voltage difference between the model bit line voltage and the reference voltage with the reference voltage to provide the voltage. 